Serial Rapidio Data Rate

RapidIO

LogiCORE IP Serial RapidIO v5.6 – SRIO Gen 1.3 with extensions for Gen 2 -5G line rate Support For the Serial RapidIO Gen 2 Xilinx LogiCORE IP, please click here.

1. The Emergence of High-Speed Serial Interfaces. With the ever-increasing demand for higher data bandwidth, wired interfaces have increased their clock rates and.

The RapidIO architecture is a high-performance packet-switched, interconnect technology. RapidIO supports messaging, read/write and cache coherency semantics.

Serial RapidIO only specifies thes e rates for both the 1x and 4x ports. data rate, which means it is not possible to identify the best setting by data rate.

Serial RapidIO Gen 2; a Flow Control Extensions Specification was released that provides congestion control for medium-rate data plane applications using the.

An Embedded System Component Network Architecture

The Growing Demand for Bandwidth

The Internet bandwidth requirements are being driven by consumers ever increasing demand for continuous Internet access and multimedia-rich web applications, which require rapid, efficient processing and transmission of data over wired or wireless media. The computing and networking industry in turn has responded by increasing microprocessor clock speeds and introducing network processors, required to support this data processing need. Increased CPU speeds, however, are only part of the solution. In a typical embedded system, the bottleneck is at the system interconnect level, i.e. the speed at which various components inside the box communicate with each other.

The RapidIO architecture eliminates this bottleneck by defining a high-performance, packet-switched, interconnect technology designed for passing data and control information between microprocessors, DSPs, communication and network processors, system memory, and peripheral devices within a system. Designed for networking and communications equipment, enterprise storage and other high-performance embedded markets, the RapidIO architecture addresses the demand for higher performance by offering the bandwidth, software independence, fault tolerance, and low latency

In September 2003, a Flow Control Extensions Specification was released that provides congestion control for medium-rate data plane applications using the RapidIO interconnect architecture. These end-to-end flow control extensions enable the immediate development of cost-effective, RapidIO-based communications applications such as media gateways, radio network controllers RNCs and routers used in mobile networks, and complement its existing link-based flow control technology.

In June, 2003, the RapidIO Trade Association announced plans to expand its application focus to fully cover data plane applications for telecommunications networks. The planned extensions will enable lower-cost standards-based products such as multiprotocol switches, 10 gigabit Ethernet switches, edge routers, SAN switches, DSLAMs and IP service switches.

The RapidIO Interconnect Architecture, designed to be compatible with the most popular integrated communications processors, host processors, and networking digital signal processors, is a high-performance, packet-switched, interconnect technology. It addresses the high-performance embedded industry s need for reliability, increased bandwidth, and faster bus speeds in an intra-system interconnect.

The RapidIO interconnect allows chip-to-chip and board-to-board communications at performance levels scaling to ten Gigabits per second and beyond. It is a low latency, memory-address based protocol that is scalable, reliable, supports multi-processing and is transparent to application software. Additionally, it has no impact on operating system software.

The RapidIO interconnect is designed for common. 25 and . 18 micron CMOS technology and to have a minimum silicon footprint for low cost FPGA based designs. The logic required to implement a RapidIO endpoint is similar in scale to a PCI-X endpoint.

The RapidIO Interconnect can also be a bridge to other bus technologies such as PCI, PCI-X, and system area networks like InfiniBand. A rich variety of features are provided in the RapidIO interconnect including high data bandwidth capability and support for high-performance I/O devices, as well as globally shared memory, message passing, and software managed programming models.

The RapidIO specification is an open standard supported by the RapidIO Trade Association, a nonprofit corporation controlled by its members. The Trade Association directs the future development and drives the adoption the RapidIO architecture. Xilinx is working very closely with Motorola to enable rapid deployment of products based on the RapidIO architecture.

Page 2 Functional Description RapidIO Dynamic Data Rate Reconfiguration Reference Design for Stratix IV GX Devices December 2010 Altera Corporation.